1. Field of the Invention
The invention relates in general to an under bump metallurgy structure and a wafer structure using the same and a method of manufacturing the wafer structure, and more particularly to an under bump metallurgy structure formed by way of electroless plating and a wafer structure using the same and a method of manufacturing the wafer structure.
2. Description of the Related Art
Of the semiconductor packaging technologies, examples of most common chip bonding technologies include flip chip bonding, wire bonding and tape automated bonding. According to these chip bonding technologies, chips and substrates are electrically connected. The flip chip bonding technology uses a solder bump as an electrically connecting medium for the chip and the substrate. Compared with the wire bonding technology and the tape automated bonding technology, the flip chip bonding technology has shorter electrical path and better electrical connection quality. Therefore, the method of using solder bump in chip bonding has been widely adopted in the field of semiconductor packaging.
According to a well-known method of manufacturing bump, an under bump metallurgy (UBM) layer is formed on a chip surface first, and the UBM layer covers a copper solder pad on the chip surface. Normally, the under bump metallurgy layer is formed by way of sputtering or electroplating. Next, the photoresist layer is coated and a photo etching process is performed, so that the dimension of the under bump metallurgy layer substantially corresponds to that of the copper solder pad. Then, the photoresist layer is stripped, and the solder paste is printed on the UBM layer. After that, the solder paste undergoes a reflowing process to form the bump. In the reflowing process, the solder particles in the solder paste are liquidfied first, and then cooled off to solidify.
Owing to the complicated process steps of the above-described method of forming a bump, the cost of the manufacturing process can not be effectively reduced. Therefore, another method for forming bump without using photo etching process is provided. The method without photo etching includes the following steps. First, a nickel layer is electroless plated onto a copper solder pad, and a palladium layer is electroless plated onto the nickel layer. Then, a wetting layer, such as a gold layer, is formed. Afterwards, a bump is formed through the printing and reflowing processes. The process of electroless plating nickel is a chemical reduction which reduces and deposits nickel ions on the catalytic surface by a reductant (such as sodium hypophosphite) of the solution. In terms of the interface reaction, the electroless plated nickel has excellent property of shielding the diffusion of copper, and therefore is widely used as a diffusion barrier in the solder bump of electronic packaging. In the step of electroless plating a nickel layer, a wafer is immersed in a plating bath which provides nickel ions from nickel sulfate (NiSO4) and uses sodium hypophosphite (NaH2PO2) as a reductant for reducing the nickel ions to nickel metal. An autocatalytic reaction by using the nickel metal as a catalytic agent is performed, so that a nickel with phosphorus layer (Ni—P) is plated onto the aluminum or copper solder pad. Such electroless plating process has the advantages of uniform layer thickness, low porosity, fine crystallization, robust hardness and good solderability. However, the electroless plating manufacturing process is susceptible to the factors such as the ingredients of the plating bath, concentration thereof, operating temperature and pH value. For example, during thermal manufacturing processes, such as reflowing the solder paste, a crystallized phosphorous-rich inter-metallic compound (IMC) is likely to form between the solder paste and the nickel layer. During the displacement reaction of electroless plating process, when a relative small nickel atom is dissolved (oxidized), two relative large gold atoms will be deposited (reduced), resulting in overall misalignment during the growth of lattice. As a result, the interface between nickel and gold generates many pores or may even contains liquid of plating bath, causing the nickel layer to be passivated and oxidized continually, which largely deteriorates the interface quality. Besides, when the nickel layer contains relative large amount of phosphorous, the solderability will be decreased. Therefore, the phosphorus contained in the nickel layer is normally controlled between 7˜9%. An interface between a bump and a nickel with phosphorus layer is taken for example below. Please refer to FIG. 1 and attachment 1 at the same time. FIG. 1 is a perspective of the interface between a bump and an electroless plated nickel layer from the prior art. Attachment 1 is a scanning electron microscopy (SEM) photo of FIG. 1. According to the scanning electron microscopy (SEM) and the ingredient analysis, a crystallized phosphorous-rich inter-metallic compound 102 is formed between the bump 103 and the nickel with phosphorus layer 101. Owing to the brittiness of the inter-metallic compound 102, the connecting point between the bump 103 and the chip therefore has a low joining strength. While soldering, molding or testing the chip, the crystallized inter-metallic compound 102 may break, hence deteriorating the yield rate and product reliability as well.